The silicon chip has become a symbol of modern electronics. Semiconductorbased devices dominate the digital electronic world, and new applications of such devices are continually being created. As these applications demand greater optimization, semiconductor devices are developed which are both smaller and faster than their predecessors.
As this optimization process continues, the physical limits of existing semiconductor technology present barriers to continued miniaturization. One such barrier is created by the necessity of the use of capacitors in these semiconductor devices to store the charge. For example, some digital memory devices typically require capacitors to retain the charge necessary to retain memory data intact. Dynamic RAMs, as such devices are called, must be refreshed periodically to prevent the data from being lost. The period of time required between such refreshes is important to computer hardware design, as more complex circuitry is required where the period is shorter.
Unfortunately, the period between required refreshes is dependent upon the capacitance of certain capacitors within the DRAM integrated circuit. Capacitance itself is related to the surface area and thickness of the capacitor, with larger and thinner capacitor surfaces providing a higher capacitance. Since there are practical limits to the minimum thickness of the capacitor, miniaturization of capacitors leads to lower capacitance and thereby a shorter period between refreshes. Since there is a minimum acceptable refresh period, some means for regaining the capacitance lost to size reduction is needed. One method for increasing the capacitance without increasing the physical dimensions of the capacitor is to utilize a material having a high dielectric constant to separate the plates of the capacitor.
A number of ferroelectric materials are known to have very high dielectric constants. Ferroelectrics such as lead zirconate titanate (PZT) and lead lanthanum zirconate titanate (PLZT) are particularly attractive in this regard, as thin films of these materials may be deposited on integrated circuits. Depending on the specific composition and manner of deposition, dielectric constants in excess of 100 are routinely achieved.
Unfortunately, these materials present a number of problems when the materials are incorporated into conventional integrated circuits. A typical ferroelectric capacitor consists of a bottom electrode, a PLZT dielectric layer, and a top electrode. The electrodes are typically constructed from Platinum. An array of such capacitors is constructed by patterning the bottom electrodes, depositing a PLZT film over the bottom electrodes, and then depositing a top layer of Platinum which is etched to form the individual top electrodes. The top surface of such a structure includes regions with exposed PLZT material and exposed areas of Platinum. The top surface of this structure is normally coated with SiO.sub.2 which provides protection from scratching and acts as an interlayer dielectric for isolating metal interconnects from the top and bottom electrodes. Metal interconnects to the top and bottom electrodes are typically provided by etching via holes in the SiO.sub.2 layer.
Unfortunately, the silicon in the SiO.sub.2 can react with the ferroelectric materials in those regions in which the materials in question are in contact. This can lead to degraded performance from the capacitor. In addition, the capacitor may show aging effects as a result of the interaction in question. Finally, the SiO.sub.2 layer has a tendency to crack when placed in contact with the Platinum electrodes. A cracked SiO.sub.2 layer is a poor substrate on which to deposit the metal interconnects.
Broadly, it is the object of the present invention to provide an improved ferroelectric based capacitor structure.
It is a further object of the present invention to eliminate the cracking that occurs when the SiO.sub.2 layer is placed in contact with Platinum electrodes.
It is a still further object of the present invention to provide a method for covering a ferroelectric layer with an SiO.sub.2 layer without encountering the SiO.sub.2 interacting with the ferroelectric material.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.